1. Field of the Invention
The present invention relates to an integrated circuit comprising a plurality; of gates which are electrically connected to each other so that predetermined logical operations can be performed, and to a combination of a plurality of integrated circuits.
2. Description of the Related Art
While there are known various types of integrated circuits, a gate array will be taken in the following description as an example of an integrated circuit. However, the present invention is not limited to a gate array. Thus, it should be understood that the gate array will be taken just as an example. FIG. 21 is a block diagram illustrating a conventional gate array. In this example shown in FIG. 21, the gate array implements a decoding-type 2-input selector circuit with an output control which Operates with the synchronizing clock signal. In FIG. 21, reference numeral 1 denotes an actually-used logic circuit area which is used to implement logical functions of the gate array. There are also shown input pins 2a and 2b for receiving output control signals; input pins 3a and 3b for receiving select signals; a clock pin 4 for receiving a synchronizing signal; output pins 5a-5d for providing the output signal of the actually-used logic circuit area 1; and NAND gates 6a-6d which perform actual logical operations.
This gate array operates as follows: when both the output control signal OE.sub.1 and OE.sub.2 provided to the input pins 2a and 2b are at a low level, all the NAND gates 6a-6d are in an active state. In contrast, if the signal OE.sub.1 is at a high level, the outputs of the NAND gates 6a and 6b are disabled. If the signal EO.sub.2 is at a high level, the outputs of the NAND gates 6c and 6d are disabled. In these disabled states, the outputs of output pins 5a and 5b, or 5c and 5d are fixed to a low level regardless of the states of the other input pins 3a and 3b and the clock pin 4. Therefore, when, both signals OE.sub.1 and OE.sub.2 are at a low level, the output signals Y.sub.1 -Y.sub.4 responsive to the select signals I.sub.1 and I.sub.2 provided to the input pins 3 a and 3b may be selected. In this situation, if both select signals I.sub.1 and I.sub.2 are at a low level, the synchronizing signal CLK being input to the clock pin 4 will appear as the output signal Y.sub.1 at the output pin 5a. If both select signals I.sub.1 and I.sub.2 are at a high level, the synchronizing signal CLK will appear at the output pin 5b. Similarly, if the select signal I.sub.1 is at a high level and the select signal I.sub.2 is at a low level, the synchronizing signal CLK will appear at the output pin 5c, and if the select signal I.sub.1 is at a low level and the select signal I.sub.2 is at a high level, the synchronizing signal CLK will appear at the output pin 5d.
The conventional technology regarding the gate array is also disclosed in U.S. Pat. No. 4,902,986 (Feb. 20, 1990).
In a conventional integrated circuit, such as a gate array described above as an example, the propagation delay time of the internal circuit varies due to a change in temperature or other reasons. As a result, when the output signal of an integrated circuit is used together with another signal, it is required to have a large margin including the variations in the propagation delay. Another problem is that a gate array cannot contain a circuit such as a delay circuit which must operate with high accuracy timing.